As dynamic random access memory (DRAM) devices become more highly integrated, the memory cells therein become smaller. More particularly, a smaller area is available for each memory cell capacitor. Because the capacitance of a capacitor is directly proportional to the surface area of the electrodes of the capacitor, there exists a need to obtain increased capacitance from capacitors occupying smaller portions of the substrate.
In a dynamic random access memory device, the operation of a memory cell improves as the capacitance of the memory cell capacitor increases. As discussed above, the memory cell capacitance is proportional to the surface area of the storage electrode. Accordingly, the surface area of the storage electrodes should be increased to increase the capacitance of the memory cell capacitor and thus the performance of the memory cell.
Storage electrode surface areas have been increased by forming storage electrodes having three-dimensional structures. For example, cylindrical and fin type storage electrode structures have been proposed. Methods for forming storage electrodes having three-dimensional structures, however, may be complex, and undesirable step differences may be produced between a cell array region and a periphery region. These step differences may be sufficiently large that photolithographically formed patterns may have reduced resolution.
Storage electrode surface areas have also been increased by forming a hemispherical grain (HSG) silicon layer on the surface of the storage electrode. Steps of a method for forming a hemispherical grained silicon layer on a storage electrode according to the prior art are illustrated in FIGS. 1 and 2. In a dynamic random access memory device, a memory cell access transistor is formed on a semiconductor substrate 1. An insulating layer 3 is then formed on the semiconductor substrate 1 and the memory cell access transistor. Moreover, a contact hole is formed through the insulating layer 3 using photolithographic and etch steps to expose a source/drain region of the memory cell access transistor in the substrate 1.
The exposed surface portions of the semiconductor substrate 1 may have a crystal structure different than that of the bulk region of the semiconductor substrate 1 as well as a higher bonding energy due to damage caused during the etch step. In particular, a dry etch step and a wet etch step may damage the exposed portion of the substrate and impurities may be absorbed from the air.
An amorphous silicon layer is formed on the insulating layer 3 wherein the amorphous silicon layer fills the contact hole. The amorphous silicon layer can be formed by reacting a silicon source gas such as silane (SiH.sub.4) or disilane (Si.sub.2 H.sub.6) with a dopant gas such as phosphine (PH.sub.3) at a temperature in the range of 480.degree. C. to 550.degree. C. At an initial stage of forming the amorphous silicon layer, a plurality of silicon nuclei may be formed at the bottom of the contact hole as indicated by the reference character A of FIG. 1. These silicon nuclei may result because the bonding energy of the surface of the semiconductor substrate 1 exposed through the contact hole may be high. The amorphous silicon layer is then patterned to provide a capacitor storage electrode 5 on the insulating layer 3 and in the contact hole. Accordingly, the capacitor storage electrode 5 is coupled to the source/drain region of the memory cell access transistor.
The structure including the capacitor storage electrode 5 is then loaded into a sealed chamber or furnace. This structure is heat processed at a temperature in the range of 600.degree. C. to 620.degree. C. and a silicon source gas is injected to form silicon nuclei on the amorphous storage electrode 5. The structure is then annealed without injecting the silicon source gas to grow the silicon nuclei thereby forming a hemispherical grained (HSG) polysilicon layer 7. This HSG polysilicon layer 7 thus increases the surface area of the amorphous silicon capacitor storage electrode 5.
The silicon nuclei formed at the bottom of the amorphous silicon lo layer adjacent the semiconductor substrate 1, however, may grow so that crystallization occurs through the amorphous silicon up to the surface of the capacitor storage electrode 5 as indicated by reference B of FIG. 2. The HSG polysilicon layer 7, however, may form only on amorphous portions of the capacitor storage electrode 5. In other words, the HSG polysilicon layer 7 may is not sufficiently form on the silicon grains B of FIG. 2 because the bonding energy of the silicon atoms within the silicon grains B may be so high that the silicon nuclei are not formed thereon. Even if silicon nuclei are formed on the silicon grains B, the silicon atoms within the silicon grains B may not migrate sufficiently so that the silicon nuclei do not grow normally.
Because the HSG polysilicon layer may not form uniformly across the storage electrode, the surface area of the storage electrode may not be sufficiently increased. Accordingly, there continues to exist a need in the art for improved methods of forming hemispherical grained silicon layers.